This invention relates to integrated circuits (IC""s), and more particularly to clock power-down detection.
Low-power and battery-operated electronic systems often are able to power down all or parts of the system to reduce power consumption. Subsystems can be partially powered down by stopping a clock input to the subsystem, or more fully powered down by asserting a power-down or enable input to the subsystem.
FIG. 1 shows a prior-art chip with separate clock and power-down inputs. Chip 10 could be a subsystem such as a memory, or part of a subsystem such as one memory chip on a memory module, or a network controller on a network card. A clock is input to chip 10, and a separate power-down signal is applied to an enable input (xcx9cEN) of chip 10. When the power-down signal is active (high), chip 10 is disabled and its power consumption is reduced. The clock to chip 10 may or may not be stopped.
Oftentimes the number of pins on a chip is limited, and using one of the few available pins for a power-down signal is undesirable. Sometimes the power-down condition can be detected by examining other pins. FIG. 2A shows detecting a stopped clock to power down a chip. Chip 10xe2x80x2 includes frequency detector 12 which receives a clock input to chip 10xe2x80x2, such as a general clock that is used elsewhere in chip 10xe2x80x2.
When the clock input to chip 10xe2x80x2 is stopped, such as when the system wishes to reduce power for the subsystem containing chip 10xe2x80x2, frequency detector 12 detects that the clock has stopped and activates an internal power-down signal. This internal power-down signal disables or shuts off various circuits in chip 10xe2x80x2, reducing its power consumption. Frequency detector 12 may activate the internal power-down signal when the frequency of the clock input falls below a threshold frequency such as 1 kHz, 1 MHz, 10 Hz, or some other value.
A problem can occur when using a frequency detector to detect a slowed or stopped clock. Another nearby clock (NB_CLK) may have a metal trace or wire parallel to the clock input to chip 10xe2x80x2 for a distance on a circuit board. When NB_CLK pulses and CLK_IN is off, a small voltage pulse may be capacitivly coupled into the clock input CLK_IN to chip 10xe2x80x2. FIG. 2B is a waveform showing capacitive coupling of a nearby clock trace that can cause false power-ups. When the nearby clock NB_CLK has a fast rising edge, a pulse can be coupled onto CLK_IN. If this pulse is sufficiently large, it can appear to the frequency detector as a clock pulse. When the frequency of the nearby clock is above the frequency detect threshold, chip 10xe2x80x2 is falsely powered back up by these clock glitches.
To avoid having such small, brief glitches falsely triggering power-up, some filtering can be added to the detector. The frequency detector then requires a certain high pulse width before triggering power-up. FIG. 3A shows a filtered clock detector. Chip 16 receives a clock input CLK_IN, which is applied to the gate of transistor 22 in detector 12xe2x80x2. When the high pulse time of CLK_IN is sufficiently large, transistor 22 discharges capacitor 20 more rapidly than resistor 24 charges it back up. Then node PS falls below the threshold of buffer 18, causing buffer 18 to drive the internal power-down signal low (inactive). When the clock stops, transistor 22 remains off and resistor 24 charges capacitor 20 above the threshold of buffer 18, which then drives the power-down signal high (active).
FIG. 3B is a waveform showing power-down detection when the high pulse is too narrow. When CLK_IN has a high time greater than the minimum, TH greater than TH(min), then the power-down signal remains low as the transistor discharges the capacitor on node PS. However, as the high pulse width decreases further, it falls below the minimum width, and PS is not sufficiently discharged by the transistor. Node PS rises in voltage above the threshold of the buffer, VT, so that the buffer drives the power-down signal PD high to initiate power-down.
Some systems may power-down the clock by leaving it in the high state rather than the low state. In that case transistor 22 remains on, keeping node PS low and preventing buffer 18 from driving the power-down signal high. FIG. 3C is a waveform showing a failure to power down when the clock is held high. The clock input CLK_IN is slowed down or stopped in the high state rather than the low state. The high pulse width is nearly or all of the entire clock period, causing TH greater than TH(min) and meeting the requirement for detecting an active (running) clock. Node PS is discharged by the transistor during the clock-high time, and stays below threshold VT. The power-down signal remains inactive, and the chip does not power down as expected.
What is desired is a clock detector that detects when the clock stops in the high or low state. A clock detector is desired that detects when the clock""s duty cycle is too high or too low and activates a power-down signal. A clock detector that does not falsely power-up a chip when glitches occur on a stopped clock line is desirable, regardless of whether the clock is stopped in the high or low state.